Archive for the ‘Test Report’ Category

Some comments on the NetworkWorld test report “How we tested Cisco’s Catalyst switch“, the SUT being a Cisco Catalyst 4500 with Supervisor 7E (Full Article):

The UPoE Effect
It’s not clear whether only one or all 8 line cards were supporting UPoE during the test.
If only a single line card was supporting UPoE, a slightly different test would be worth running; in which test traffic across 7 non-UPoE cards were compared against the exact same traffic but with the UPoE card replacing a non-UPoE card.
A comparison of the resulting data would highlight any effect on traffic attributable to UPoE being active.

Performance & Optional Tests
The duration of the performance is not defined in the test report. The report states that the traffic pattern consisted of at least 1 burst of 60s duration per traffic type (layer-2 unicast, layer-2 multicast, IPv4 & IPv6). I assume the test traffic included micro-bursts of learning frames in order to populate the MAC address table before generating the latency test traffic.
An available & interesting option given the traffic generators used would be to allow the traffic to continue in cycles where the gap between bursts exceeds the address ageing time. This would stress the MAC learning processes & test memory allocation/re-allocation. A plot of CPU usage versus time on the SUP over the course of multiple cycles would highlight how stable these processes are under this stress.
Cisco quote the 4500 Supervisor 7E MAC address learning rate at 20K/s (, hence can we assume this scales to the full 55K being learned in 2.45s.. This test would manifest any gradual drift in the time taken for MAC learning at scale, hence indicating (or not) any buried memory management or process-locking issues.

Supervisor 7E Throughput, Conclusions & Underlying Assumptions
Cisco quote the Supervisor 7E’s IPv4 throughput as 250M packets per second ( The test report author states  “The new Supervisor 7-E card, like the 6-E before it, has a processing limit of 250 million frames per second, and that in turn limits non-blocking performance to 167 out of a possible 384 Gigabit Ethernet ports.”
It would be interesting to understand the assumptions underlying this conclusion.
However, the author’s point; “Given that wire-speed “merchant silicon” ASICs have been around for 10 years or so, it’s always surprising to see any new switch with blocking performance” is well-made.


  • I review for the O'Reilly Blogger Review Program

%d bloggers like this: